This invention concerns electronic data processing systems, and more particularly a method and apparatus for controlling the transfer of data between a SCSI bus of an electronic data processing system and a peripheral storage device.
The problem of transferring data from a peripheral storage media such as: punched cards, punched tape, magnetic tape, magnetic drums, magnetic disks, and optical disks has always been a major consideration as the technology of automatic data processing systems advanced. Peripheral storage media were required to increase in data handling rate, decrease in data storage density, and improve the cost per unit increase of the data storage density with respect to the data handling performance in order to remain attractive in the marketplace. These three aspects of the peripheral storage system had to not only improve together, but also had to keep pace with the rapid improvements in the related technology of automatic data processing systems.
With the completion of the ANSI X3.131-1986 standard for a small computer system interface (SCSI), the small computer industry set the goals for the next generation of small system peripheral interfaces and the interaction of peripheral storage media with such interfaces. The SCSI standard paves the way for a very high data transfer rate between the SCSI bus and a peripheral storage device, such as a Winchester disk system. To achieve these higher rates, a high speed method and apparatus for data transfer is needed, which does not exist in the electronic data processing field.
U.S. Pat. No. 4,612,613 issued Sept. 16, 1986, discloses a FIFO buffer queue (607) in FIG. 6 which is part of a disk drive control apparatus. This FIFO buffer transfers both control information and data between the disk memories (119n-119o) and the controller (107 See FIG. 1). The FIFO buffer 607 is a single buffer which is sixteen bits wide by 10 words deep (See Column 40, Line 48 et seq.), which is controlled by an apparatus controller 609 (Column 40, Line 42 et seq.) to sort out the destinations of each entry stored in the FIFO buffer 607. The operation of FIFO buffer 607 is detailed at Column 13, Line 21 through Column 14, Line 27. Since the control information and data information are interleaved in this single FIFO buffer, the apparatus control 609 had to be rather complex in order to select and transfer the information to its proper destination. Such a complex buffer control method either slows things down, or leads to very high speed and very high cost control circuitry.
U.S. Pat. No. 3,673,576 issued June 27, 1972, discloses a programmable computer peripheral interface. The interface performs the function of a direct memory access controller which either receives data from the computer main memory or transmits data to the computer main memory during an interrupt condition of the central processing unit. This peripheral interface would only transfer blocks of individual words either to or from the peripheral device and perform any word length changes such as from sixteen to thirty-two bits words required in the process. Such a method and apparatus would be far too slow to transfer multiple blocks of sectors of bytes such as transferred between a SCSI bus and a Winchester hard disk device.
U.S. Pat. Nos. 4,467,411 issued Aug. 21, 1984 and 4,428,064 issued Jan. 24, 1984, which are both commonly assigned to IBM, disclose various control aspects for a managed buffer of a magnetic tape storage device. These two patents disclose devices which control data buffers according to a most-recently-used/least-recently-used (MRU/LRU) algorithm. This algorithm stores and retains large amounts of data that is related to the last data requested because statistical studies have shown that the next word of information requested by a central processing unit has a very good probability of being closely related to the previous word of information requested. Such probabilities are used as speed up techniques to compensate for the slower data rate of the magnetic tape drive. Such complex buffer management through prioritizing the data according to MRU/LRU considerations are obviated by the data availability of hard disk drives, thus, opening the way for simpler and faster methods of operating data transfer buffers.
Another patent of interest is U.S. Pat. No. 4,349,875 issued Sept. 14, 1982, which discloses a buffer storage control apparatus which uses a variation of the least-recently-used algorithm discussed previously to the control of the data transfers to or from its buffers. This variation of the LRU algorithm, like the MRU/LRU algorithm, is unnecessary when a high speed storage device is used since the LRU algorithm is used to compensate for slower data storage devices.
It is an object of this invention to provide a method for controlling the transfer of information between a SCSI bus and a high speed data storage device.
It is a further object of this invention to provide a method for controlling data transfers to the SCSI bus from one buffer, while another buffer is available to receive data from the high speed storage device at the same time to attain a high data transfer rate.
It is a further object of this invention to provide a method for controlling data transfers from the SCSI bus to one buffer, while another buffer is available to send data to the high speed storage device at the same time to attain a high data transfer rate.
It is a further object of this invention to provide a finite state machine apparatus for controlling high speed data transfers with the multiple buffers.